The present invention relates generally to integrated circuits, and more particularly to method and circuitry for performing automatic power on reset of an integrated circuit (IC).
An IC is typically made up of various circuit blocks that operate together to provide the required functionality. In many applications, an IC may require an initialization routine for proper operation of the circuits upon power up. The initialization routine generally ensures that, for example, the power supply voltages have reached an acceptable threshold, the clock signal(s) has settled, internal registers have been reset to their proper values, and so on.
Most IC power on reset or initialization routines use a level detect circuit that monitors the power supply voltage level and enables operation of various blocks within the integrated circuit when the voltage level exceeds a predetermined threshold. Today""s more complex ICs often integrate different technologies and different types of circuitry on the same die, and tend to operate at lower supply voltage levels, and with wider supply voltage ranges. Conventional power on detect circuits fail to adequately meet the requirements of such circuits. Further, in some application, an IC may be required to operate from more than one clock sources, in which case the initialization routine is more complicated because of the need to select the appropriate clock and to determine when the respective clocks have settled so that only valid clock signals are used.
As can be seen, reliable and efficient techniques for performing automatic power on reset for these integrated circuits are highly desirable.
The invention provides method and circuitry for performing automatic power on reset for an integrated circuit. In one embodiment, the present invention provides a robust power on detect circuit that operates effectively with a wide ranging power supply voltage that may ramp up more slowly. In another embodiment, the present invention provides a power on reset routine for an IC that may have a number of different clock sources.
Accordingly, in one embodiment, the present invention provides a method for resetting an integrated circuit upon power up, the method including the steps of: detecting a voltage level on a power supply node and generating a power on detect signal when the voltage level reaches a predetermined level; asserting a reset signal in response to the power on detect signal, the reset signal disabling a plurality of internal circuitry except at least an internal oscillator; counting a first predetermined number of cycles of an oscillating output of the internal oscillator; reading contents of a first register to select a clock source, at about the completion of the counting step; if the contents of the first register indicate selection of the internal oscillator, coupling the oscillating output to system clock and de-asserting the reset signal; and if the contents of the first register indicate selection of a second clock source other than the internal oscillator, coupling an output of the second clock source to system clock.
In another embodiment, the present invention provides an integrated circuit including: a controller; a clock circuit coupled to the controller and configured to select between a plurality of clock sources including an internal oscillator; a voltage sensing circuit configured to detect a voltage level on a power supply node; a global reset circuit coupled to the voltage sensing circuit and configured to generate a global reset signal that, when activated, resets most of the integrated circuit except for at least the internal oscillator; and a register coupled to the clock circuit, and configured to store clock information, wherein, when the voltage sensing circuit detects a power up condition, the internal oscillator automatically runs for a predetermined number of cycles before the contents of the register are read to select one of the plurality of clock sources.
In yet another embodiment, the present invention provides a power on detect circuit for signaling a power on condition in response to a voltage level on a power supply node, the power on detect circuit including a diode-coupled transistor having its gate-drain terminal coupled to the power supply node via a switch circuit; a weak transistor having a gate terminal coupled to the gate-drain terminal of the diode-coupled transistor; a first source/drain terminal coupled to the power supply node, and a second source/drain terminal coupled to ground via a delay capacitance; a Schmidt trigger circuit having an input coupled to the second source/drain terminal of the weak transistor; a first inverter having an input coupled to an output of the Schmidt trigger, and an output coupled to the switch circuit; a second inverter having an input coupled to an output of the first inverter, and an output coupled to carry a power on reset output signal.
A better understanding of the nature and advantages of the automatic power on reset method and circuitry of the present invention will be gained by referring to the following detailed description and accompanying drawings.